In many applications, it is desirable to disable the output of an amplifier. For example, in a memory device, wherein different amplifiers drive the same data output line in different time periods, the output of one amplifier must be disabled to allow another amplifier to drive the line. Another example is an amplifier in a memory device with a bidirectional data input/output line, wherein the output of the amplifier may be disabled after each data reading operation to allow a data writing operation to be performed.
As illustrated in FIG. 1 of the drawings, a memory chip 10 may have a bidirectional data input/output line 12 for reading data from a memory array 14 and writing data to the memory array 14. An address and control signal generator 16 receives external address and control signals from an address and control signal input 18 to provide control of data reading and writing operations. A master clock input 20 supplies a clock generator 22 with an external master clock to control timing of data reading and writing operations. Input data are supplied to the memory array 14 from the data input/output line 12 via data input buffers/latches 24.
When a cell of the memory array is addressed for data reading, the data stored in the addressed cell is amplified through the memory cell sense amplifier. The output of the memory cell sense amplifier may be connected to a preamplifier 26 that supplies a main amplifier 28 with a pre-amplified data signal. The main amplifier 28 may have an input IN for receiving the data signal, and complementary outputs OUT and OUTC. An output driver composed of power MOS transistors 30 and 32 coupled in series between power sources VSSQ and VDDQ may be connected to the outputs OUT and OUTC for driving the data input/output line 12.
A data reading operation may be initiated for example by a raising edge of the external master clock. In response to the raising edge, the clock generator 22 controls the address and control signal generator 16 to produce an output enable signal ZOE supplied to a ZOE input of the main amplifier 28 to initiate data output from the memory input/output line 12.
The next edge of the external master clock may initiate a no operation cycle, in which the address and control signal generator 16 switches the logic level of the ZOE signal. Alternatively, a data writing operation may be decoded to switch the ZOE signal. When the ZOE signal is switched, the outputs OUT and OUTC of the main amplifier 28 are disabled to place the output driver into a floating or high impedance state before writing data via the input/output line 16.
Propagation and switching delays between the ZOE input and the outputs of the main amplifier 28 result in a time delay between switching the logic level of the output enable signal ZOE and disabling the outputs of the main amplifier 28. This time delay is called the output disable time (t.sub.HZ).
In high-frequency applications, for example, at a 200 MHz rate, a clock cycle is reduced to 5 ns. At such rates, it is critical to reduce the output disable time of the main amplifier.
Therefore, it would be desirable to provide an amplifier having the output disable time reduced compared to conventional amplifiers.